adaptive fir filter using lms algorithm for an area efficient design
R Ranjitha,R.Rajeswari
Published in International Journal of Advanced Research in Electronics, Communication & Instrumentation Engineering and Development
ISSN: 2347 -7210 Impact Factor:1.9 Volume:1 Issue:2 Year: 08 February,2014 Pages:61-70
Abstract
This briefly presents a novel pipelined architecture for low-power and low-area implementation of Adaptive filter based on distributed arithmetic (DA). The conventional adder-based shift accumulation for DA-based inner-product computation is replaced by conditional signed carry-save accumulation in order to reduce the sampling period and area complexity. Reduction of power consumption is achieved in the proposed design by using a fast bit clock for carry-save accumulation but a much slower clock for all other operations. It involves the same number of multiplexers, smaller LUT, and nearly half the number of adders compared to the existing DA-based design. By changing the inner block we are going to achieve low area and low power .So our previous DA-based adaptive filter in average for filter lengths N=4and N=16 Implemented.
Kewords
Adaptive filter, Distributed arithmetic, carry save adder.
Reference
[1] Abdul Qayyum and Moona Mazher,“ Design of Programmable Efficient Finite Impulse Response Filter Base On Distributive Arithmetic Algorithm", Volume 1,December 2012 . [2] Basant K. Mohanty, Senior Member, IEEE, and Pramod Kuma Meher, Senior Member, IEEE Senior Member, IEEE ‘A High- Performance Energy-Efficient Architecture for FIR Adaptive Filter Based on New Distribute Arithmetic Formulation of Block LMS Algorithm’ VOL. 61, NO. 4, FEBRUARY 15, 2013 [3] D. J. Allred, H. Yoo, V. Krishnan, W. Huang, and D. V. Anderson “LMS adaptive filters using distributed arithmetic for high throughput IEEE Trascircuit Syst. I, Reg. Papers, vol.52, no. 7,pp. 1327–1337,Jul. 2005. [4] M. D. Meyer and P. Agrawal, “A modular pipelined implementation of a delayed LMS transversal adaptive filter,” in Proc. IEEE In Symp Circuit Syst., May 1990, pp. 1943–1946. [5] N.V.Sai Rupa, M.Ram Mohan Reddy, “Memory Efficient Architecture For High Speed Fir Filter Using Distribute Arithmetic Volume 4, Issue 9, September-2013". [6] P. K. Meher and S. Y. Park, “High-throughput pipelined realization of adaptive FIR filter based on distributed arithmetic,” in VLSI Symp. Tech. Dig., Oct. 2011, pp. 428–433. [7] P.Sravanthi, CH. Srinivasa Rao, S.Madhava Raeo ,”A Novel Approach of Area-Efficient FIR Filter Design Using Distributed Arithmetic with Decomposed LUT” Volume 7, Issue 2 (Jul. - Aug. 2013), PP 1318 [8] R. Guo and L.S. DeBrunner, “A novel adaptive filter Implementation using distributed arithmetic,” in Proc Asilomar Conf. Signals, Syst., Comput., Nov. 2011, pp.160–164. [9] P.Sravanthi, CH.Srinivasa Rao, S.Madhava Rae ,”A Novel Approach of Area-Efficient FIR Filter Design Using Distributed Arithmetic with Decomposed LUT Volume 7, Issue 2 (Jul. - Aug. 2013), PP 1318 [10] Patrick Longa, Ali Miri, "Area-Efficient Fir Filter Design on FPGAs using Distributed Arithmetic" IEEE International Symposium on Signal Processing and Information Technology, pp:248-252,2006 [11] R. Guo and L. S. DeBrunner, “Two high-performance adaptive Filter ’' Syst. II, Exp. Briefs, vol. 58, no. 9, pp. 600–604, Sep. 2011. [12] R. Guo and L. S. DeBrunner, “A novel adaptive filter Implementation using distributed arithmetic, “in Proc Asilomar Conf.Signals,Syst., Computer., Nov. 2011, pp.160–164. [13] S. Haykin and B. Widrow, “Least-Mean-Square Adaptive Filters,” Hoboken, NJ, USA: Wiley, 2003. [14] Sangyun Hwang, Gunhee Han,Sungho Kang, Jaeseok Kim, "New Distributed Arithmetic Algorithm for Low-Power FIR Filter Implementation", IEEE Signal Processing Letters, Vol.11, No5, pp:463-466,May, 2004 [15] S. A. White, “Applications of distributed arithmetic to digital signal processing: A tutorial review,” IEEE ASSP Mag., vol. 6, pp. 4–19, Jul. 1989.
