synthesis of low-power area efficient constant multiplier architecture for reconfigurable fir filter using hybrid form
Nanthini,Ganesamoorthy
Published in International Journal of Advanced Research in Electronics, Communication & Instrumentation Engineering and Development
ISSN: 2347 -7210 Impact Factor:1.9 Volume:3 Issue:1 Year: 05 July,2016 Pages:89-94
Abstract
The design of low power and area efficient high performance DSP system. FIR digital filters are used in DSP by the stability, linear phase for fewer finite precision error and efficient implementation for different applications. Aim of getting reliable operation of these filters are protected using the eliminate common sub expression. Therefore FIR filter is largely dominated to the multiplication of input samples with filter coefficients using different algorithms. The reconfigurable FIR filter design increases in the delay are replicating the hardware. The multiple number of inputs gets processed parallel and same time generating multiple number of outputs and disadvantage of increased area in the design. To overcome this disadvantage for sense of retaining these such advantage of the hardware efficient reconfigurable filter structure is proposed by using VHBCSE algorithm. The least-mean- square (LMS) adaptive filter are deriving its Architectures for high-speed and low-complexity implementation. The direct-form LMS adaptive filter has nearly the same critical path are transpose-form counterpart but provides much faster convergence and lower register complexity. In this paper proposed in the Hybrid form of VHBCSE algorithm in the multiplier circuit. Further power, area and delay are reduced by replacing adder by square root select adder.
Kewords
Reconfigurable FIR filter, VHBCSE algorithm, BCSE, Square root select adder, LMS, Hybrid form
Reference
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