bira for word oriented memories using parallel prefix algorithm.
C. Bhaskar,K. Jeyaprakasam
Published in International Journal of Advanced Research in Electrical and Electronics Engineering
ISSN: 2321-4775 Impact Factor:1.6 Volume:1 Issue:2 Year: 08 November,2013 Pages:58-65
Abstract
This paper presents a built-in self repair analyzer(BIRA) with the optimal repair rate for ingmemory arrays with redundancy. The proposed method requires only a single test, even in the worst case. By performing the must- repair analysis on the fly during the test, it selectively stores fault addresses, and the final analysis to find a solution is performed on the stored fault addresses. To enumerate all possible solutions, existing techniques use depth first search using a stack and a finite-state machine. Instead, we propose a new algorithm and its combinational circuit implementation. Since our formulation for the circuit allows us to use the parallel prefix algorithm, it can be configured in various ways to meet area and test time requirements. The total area of our infrastructure is dominated by the number of content addressable memory entries to store the fault addresses, and it only grows quadratically with respect to the number of repair elements. The infrastructure is also extended to support various types of word-oriented memories by using pre computation CAM.
Kewords
Built-in self repair (BISR), memory test, Built in repair analyzer(BIRA).
Reference
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